By Junjie Wu, Lian Li
This publication constitutes the refereed court cases of the eleventh Annual convention on complex computing device structure, ACA 2016, held in Weihai, China, in August 2016.
The 17 revised complete papers awarded have been rigorously reviewed and chosen from 89 submissions. The papers tackle matters corresponding to processors and circuits; excessive functionality computing; GPUs and accelerators; cloud and knowledge facilities; strength and reliability; intelligence computing and cellular computing.
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Additional info for Advanced Computer Architecture: 11th Conference, ACA 2016, Weihai, China, August 22-23, 2016, Proceedings
8. Performance comparison between baseline and 3D DRAM Cache system Power Comparison. In this section, we analysis the power consumption of the proposed design, including dynamic power and leakage power. Dynamic power results from writing and reading operations, which is determined by the total amount of the two kinds of operation. Leakage power comes from the leakage current of DRAM cells. From the results of SPEC2006, it can be seen that for last level cache, the number of writing and reading operations are not very large, thus contributing to the fact that the dynamic power consumption of our design, which is shown in Fig.
988–993. ACM (2012) 12. : Online memory compression for embedded systems. ACM Trans. Embed. Comput. Syst. 9, 1–30 (2010) 13. : The ﬁlter cache: an energy eﬃcient memory structure. In: 30th International symposium on Microarchitecture (MICRO), pp. 184–193 (1997) 14. : Non-uniform power access in large caches with low-swing wires. In: International Conference on High Performance Computing (HiPC). IEEE, pp. 59–68 (2009) 15. : Compressed tag architecture for low-power embedded cache systems. J. Syst.
The concentrated method means that each of the 16 interposer nodes connects four nodes on the CPU die. There are totally 8 nodes of memory controllers on left and right sides of the interposer network. Each one connects a nearby interposer node. Figure 2 also shows two types of interposer implementations. In the near term, passive type without active devices in the interposer is a practical way, while active interposer is more likely to be a 3D integrated way. That is to say all logic/gates are placed on the CPU die and 42 mNode C.
Advanced Computer Architecture: 11th Conference, ACA 2016, Weihai, China, August 22-23, 2016, Proceedings by Junjie Wu, Lian Li